class CPU

Defined in:

cpu.cr
irqs.cr

Constructors

Instance Method Summary

Constructor Detail

def self.new(mem : Memory) #

[View source]

Instance Method Detail

def adc(operand2) #

[View source]
def add(operand2) #

[View source]
def addHL(operand2 : UInt16) #

[View source]
def and(operand2) #

[View source]
def bit(opcode) #

[View source]
def call(opcode) #

[View source]
def cp(operand2) #

[View source]
def cycles : Int32 #

[View source]
def cycles=(cycles : Int32) #

[View source]
def dec(num) #

[View source]
def dispatchInterrupt(irqVector : UInt16) #

[View source]
def execute_CB #

[View source]
def execute_opcode(opcode) #

[View source]
def executeInstruction #

[View source]
def getCondition(op, isJMP = false) #

[View source]
def getRegister(val) : UInt8 #

[View source]
def handleInterrupts #

[View source]
def inc(num) #

[View source]
def jmp(opcode) #

[View source]
def jr(opcode) #

[View source]
def nextByte #

[View source]
def nextWord #

[View source]
def or(operand2) #

[View source]
def pop #

[View source]
def push(val) #

[View source]
def res(opcode) #

[View source]
def ret(opcode) #

[View source]
def rl(opcode) #

[View source]
def rlc(opcode) #

[View source]
def rr(opcode) #

[View source]
def rrc(opcode) #

[View source]
def sbc(operand2) #

[View source]
def set(opcode) #

[View source]
def setRegister(registerNum, value) #

[View source]
def sla(opcode) #

[View source]
def sra(opcode) #

[View source]
def srl(opcode) #

[View source]
def sub(operand2) #

[View source]
def swap(opcode) #

[View source]
def total_cycles : Int32 #

[View source]
def total_cycles=(total_cycles : Int32) #

[View source]
def xor(operand2) #

[View source]