class CPU

Defined in:

cpu.cr

Constant Summary

ADD = StaticArray[F1, F2, MC::IO | MC::MI, MC::RO | MC::BI, (MC::EO | MC::AI) | MC::FI]
ADI = StaticArray[F1, F2, MC::IO | MC::BI, (MC::EO | MC::AI) | MC::FI, MC::None]
CMP = StaticArray[F1, F2, MC::IO | MC::MI, ((MC::RO | MC::BI) | MC::SU) | MC::FI, MC::None]
F1 = MC::CO | MC::MI

Fetch instruction microcode

F2 = (MC::RO | MC::II) | MC::CE
HLT = StaticArray[F1, F2, MC::HLT, MC::None, MC::None]
JC = StaticArray[F1, F2, MC::IO | MC::JC, MC::None, MC::None]
JMP = StaticArray[F1, F2, MC::IO | MC::J, MC::None, MC::None]
JPA = StaticArray[F1, F2, MC::AO | MC::J, MC::None, MC::None]
JZ = StaticArray[F1, F2, MC::IO | MC::JZ, MC::None, MC::None]
LABEL_REGEX = /^(?<label>[a-z\_\d]+)\:/i
LDA = StaticArray[F1, F2, MC::IO | MC::MI, MC::RO | MC::AI, MC::None]
LDI = StaticArray[F1, F2, MC::IO | MC::AI, MC::None, MC::None]
LSR = StaticArray[F1, F2, MC::SR | MC::FI, MC::None, MC::None]
NOP = StaticArray[F1, F2, MC::None, MC::None, MC::None]

Opcodes

OUT = StaticArray[F1, F2, MC::AO | MC::OI, MC::None, MC::None]
ROM = Slice[NOP, LDA, ADD, SUB, STA, LDI, JMP, JC, JZ, ADI, JPA, CMP, LSR, SBI, OUT, HLT]

Set opcodes in micro-code ROM

SBI = StaticArray[F1, F2, MC::IO | MC::BI, ((MC::EO | MC::SU) | MC::AI) | MC::FI, MC::None]
STA = StaticArray[F1, F2, MC::IO | MC::MI, MC::AO | MC::RI, MC::None]
SUB = StaticArray[F1, F2, MC::IO | MC::MI, MC::RO | MC::BI, ((MC::EO | MC::AI) | MC::SU) | MC::FI]
SYM_REGEX = /\:(?<label>[a-z\_\d]+)/i

Constructors

Class Method Summary

Instance Method Summary

Constructor Detail

def self.new(prog : String, options : Options | Nil = nil) #

Initialize from un-assembled program


[View source]
def self.new(ram : Bytes, options : Options | Nil = nil) #

Initialize from assembled program


[View source]

Class Method Detail

def self.asm(line : String) #

Assemble instruction


[View source]
def self.assemble(prog : String) #

Assemble a program


[View source]
def self.dasm(instr : UInt8) #

Disassemble instruction


[View source]

Instance Method Detail

def address : UInt8 #

[View source]
def address=(address : UInt8) #

[View source]
def bus : UInt8 #

[View source]
def bus_receive #

[View source]
def bus_transfer #

Based on the control word, transfer data onto the bus


[View source]
def control : MC #

[View source]
def flags #

Get the current state of the flags Note: this is latched to @reg_f on MC::FI


[View source]
def mc_step : UInt8 #

[View source]
def options : Options #

[View source]
def options=(options : Options) #

[View source]
def print_state #

[View source]
def program_counter : UInt8 #

[View source]
def ram : Bytes #

[View source]
def ram=(ram : Bytes) #

[View source]
def reg_a : UInt8 #

[View source]
def reg_b : UInt8 #

[View source]
def reg_e #

ALU


[View source]
def reg_f : Flags #

[View source]
def reg_i : UInt8 #

[View source]
def reg_o : UInt8 #

[View source]
def run(&) #

Run the main loop


[View source]
def run #

[View source]
def set_instruction #

Fetch an instruction and increment the micro-code step


[View source]
def step #

[View source]