def
add_imm(dr : UInt16, src1 : UInt16, val : UInt16) : UInt16
#
def
add_reg(dr : UInt16, src1 : UInt16, src2 : UInt16) : UInt16
#
def
and_imm(dr : UInt16, src1 : UInt16, val : UInt16) : UInt16
#
def
and_reg(dr : UInt16, src1 : UInt16, src2 : UInt16) : UInt16
#
def
branch(condition : UInt16, offset : UInt16)
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def
jump(baser : UInt16) : UInt16
#
def
jump_to_subroutine_direct(baser : UInt16) : UInt16
#
def
jump_to_subroutine_offset(offset : UInt16) : UInt16
#
def
load(dr : UInt16, offset : UInt16) : UInt16
#
def
load_effective_address(dr : UInt16, offset : UInt16) : UInt16
#
def
load_from_register(dr : UInt16, baser : UInt16, offset : UInt16) : UInt16
#
def
load_indirect(dr : UInt16, offset : UInt16) : UInt16
#
def
not(dr : UInt16, src : UInt16) : UInt16
#
def
store(source : UInt16, offset : UInt16) : UInt16
#
def
store_from_register(source : UInt16, baser : UInt16, offset : UInt16) : UInt16
#
def
store_indirect(source : UInt16, offset : UInt16) : UInt16
#
def
trap(vector_num : UInt16) : UInt16
#