module RiSC16

Overview

multi column output address, (if pseudo/data: source, if not first instruction in pseudo, then //.), instruction (source or disassembled, if data the word as it is), (compressed previous and current comments) we show all the same address LOC in another window (to complete the compressed) ex: 0x0000 | start | movi r1 :truc_machin | lui r1 0x???? | # this is a movi instr.... ex: 0x0001 | | --- | addi r1 r1 0x???? | ---

another window: This is a movi instruction. It load the upper part, then add the lower part

Direct including types

Defined in:

cli.cr
debugger/curses.cr
debugger/debugger.cr
risc16.cr

Constant Summary

DEFAULT_RAM_START = 0_u16
MAX_IMMEDIATE = 127_u16
MAX_MEMORY_SIZE = 1 + UInt16::MAX
REGISTER_COUNT = 8

Register 0 is always zero. Write are discarded.

VERSION = {{ (`shards version`).chomp.stringify }}